Manufacturing method of anti-punch-through semiconductor device

ABSTRACT

An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of prior filed applicationSer. No. 11/164,825, filed on Dec. 7, 2005, now allowed, which claimsthe priority benefit of Taiwan application serial no. 94122056, filed onJun. 30, 2005. The entirety of each of the above-mentioned patentapplications is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a semiconductor device and amanufacturing method thereof. More particularly, the present inventionrelates to an anti-punch-through semiconductor device and amanufacturing method thereof.

2. Description of Related Art

Along with the rapid development of the integrated circuit industry andthe trend of high integration, the size of the entire circuit device isforced to be minimized to meet the requirement. When the size of thesemiconductor reduces gradually, the distance between devices alsorelatively reduces. When the distance reduces to some degree, theprocess problem due to the high integration of device may occur.Therefore, it is a common objective in the industry to produce asemiconductor device with small size, high integration and high quality.

FIG. 1 is a schematic cross-sectional view of a conventional trenchdevice. Referring to FIG. 1A, a plurality of trenches 102 is formed inthe substrate 100, and the trench device is disposed in the trench 102.The trench devices are trench memories, and the trench memories includesa floating gate 104, a dielectric layer 106, and a control gate 108.Moreover, the trench device further includes a source/drain region 110disposed in the substrate under the floating gate 104, the dielectriclayer 106 and the control gate 108.

However, along with increased integration, in the process of forming thegate made of doped polysilicon, the dopant may diffuse into thesource/drain region 110 to extend the region, which may easily cause theabnormal electric punch-through in the adjacent source/drain regions110. The problem of the electric punch-through may cause abnormalelectric connection between adjacent trench devices, which may result inlow operation speed and low performance efficiency, and even short oropen circuit of the devices. Accordingly, the yield and reliability ofthe whole process are adversely affected.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a manufacturing methodof an anti-punch-through semiconductor device, wherein an isolationregion can be formed between adjacent source/drain regions to avoidelectric punch-through between the devices from affecting theperformance efficiency of the devices.

Another objective of the present invention is to provide ananti-punch-through semiconductor device, wherein, the isolation regionbetween the source/gate regions can avoid the electric punch-throughbetween the devices.

The present invention provides a manufacturing method ofanti-punch-through semiconductor device. First, a substrate is provided.Next, an insulation layer is formed on the substrate. Next, theinsulation layer is patterned to form a plurality of isolation regions.Next, a silicon layer is formed on the substrate to cover the isolationregion. Next, a trench is formed between each adjacent isolation region.Thereafter, a trench device is formed in each trench. Moreover, thetrench device further includes a source/drain region formed in thesilicon layer under the trench and between two adjacent isolationregions.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, the material ofthe insulation layer is, for example, silicon oxide.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, the thickness ofthe insulation layer is, for example, about 100 Å-1000 Å.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, the shape of theisolation region includes block or parallel stripes.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, the method offorming the source/drain region is, for example, ion-implanting method.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, the trench deviceis, for example, a trench memory.

In the manufacturing method of anti-punch-through semiconductor deviceaccording to the embodiment of the present invention, after the trenchmemory is formed, a dielectric layer is formed on the silicon layer tocover the trench memory, and a conductive layer is formed on thedielectric layer.

The present invention also provides an anti-punch-through semiconductordevice, comprising a substrate, a plurality of trench devices and atleast one insulation region. The trench device is disposed in thesubstrate, wherein the trench device includes a source/drain region, andthe source/drain region is disposed in the bottom of the trench device.The insulation layer is disposed in the substrate and between thesource/drain regions of each trench device.

According to the anti-punch-through semiconductor device in theembodiment of the present invention, the thickness of the insulationlayer is, for example, about 100 Å-1000 Å.

According to the anti-punch-through semiconductor device in theembodiment of the present invention, the material of the insulationlayer is, for example, silicon oxide.

According to the anti-punch-through semiconductor device in theembodiment of the present invention, the shape of the isolation regionincludes block or parallel stripes.

According to the anti-punch-through semiconductor device in theembodiment of the present invention, the trench device is, for example,a trench memory.

In the present invention, an isolation region is formed between twoadjacent trench devices, so as to avoid adjacent source/drain regionsduring the ion-implanting process of forming the doped polysilicon fromthe electric punch-though as the dopant diffuses into the source/drainregion to extend the region. And, the problem of the low operation speedand low performance efficiency due to the electric punch-through andreduced yield and reliability of the whole process, can also be avoided.

In order to the make the aforementioned and other objects, features andadvantages of the present invention comprehensible, a preferredembodiment accompanied with figures is described in detail below.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a conventional trenchdevice.

FIG. 2A to FIG. 2G are cross-sectional views showing the flowchart offabricating the anti-punch-through semiconductor device.

DESCRIPTION OF EMBODIMENTS

FIG. 2A to FIG. 2G are cross-sectional views showing the flowcharts ofmanufacturing the anti-punch-through semiconductor device according tothe embodiment of the present invention. The trench memory is describedin the following as an example.

First, referring to FIG. 2A, a substrate 200 is provided, and thesubstrate 200 is, for example, a silicon substrate. Next, an insulationlayer 202 is formed on the substrate 200. Wherein, the material of theinsulation layer is, for example, silicon oxide, and the thickness ofthe insulation layer 202 is about 100 Å-1000 Å, and the forming methodis, for example, a chemical vapor deposition process.

Next, referring to FIG. 2B, the insulation layer 202 is patterned byphotolithography process and etching process, and an isolation region204 is formed on the substrate 200. Note that the isolation region isdifferent from the shallow trench isolation structure used to form theactive region. The isolation region of the present invention is formeddeeper in the substrate than the shallow trench isolation structure.Moreover, the shape of the isolation region 204 includes block orparallel stripes.

Next, referring to FIG. 2B, a silicon layer 206 is formed on thesubstrate 200 to cover the isolation region 204. Wherein, the method offorming the silicon layer 206 is, for example, a chemical vapordeposition process. Next, the silicon layer 206 is planarized, and themethod of the planarization is, for example, a chemical mechanicalpolishing process. Next, a patterned mask layer 208 is formed on thesilicon layer 206. Wherein, the material of the patterned mask layer 208is, for example, silicon nitride. Thereafter, the silicon layer 206 isetched to form the trench 210 in the silicon layer 206 between twoadjacent isolation regions 204 by using the patterned mask layer 208 asa mask.

Next, referring to FIG. 2C, a tunnel oxide layer 212 is formed on thesurface of the trench 210. Wherein, the material of the tunnel oxidelayer 212 is, for example, silicon oxide, and the method of forming thetunnel oxide layer 212 is, for example, a thermal oxidation process.Next, a conductive layer 214 is formed on the silicon layer 206 andfills in the trench 210. Wherein, the material of the conductive layer214 is, for example, doped polysilicon, and the forming method is, forexample, by performing an ion-planting process after a non-dopedpolysilicon layer is formed in a chemical vapor deposition process.

Next, referring to FIG. 2D, the conductive layer 214 is removed from thepatterned mask layer 208. Wherein, the removing method is, for example,a chemical mechanical polishing process. Next, an etching back processis performed to etch a part of conductive layer 214, so that the top ofthe conductive layer 214 is higher than the surface of the silicon layer206 and lower than the surface of the patterned mask layer 208. Next, aspacer 216 is formed to cover a part of the surface of the conductivelayer 214. Wherein, the method of forming the spacer 216 is, forexample, by forming an insulation material layer (not shown), thenremoving a part of the insulation material layer in a non-isotropicetching process.

Next, referring to FIG. 2E, an etching process is performed to form afloating gate 218 on the sidewall of the trench 210 by using thepatterned mask layer 208 and the spacer 216 as the mask. Next, asource/drain region 220 is formed in the substrate 200 on the bottom ofthe trench 210, and the source/drain region 220 is disposed between twoadjacent isolation regions 204. Wherein, the method of forming thesource/drain region 220 is, for example, an ion-planting process. Next,a dielectric layer 222 is formed on the substrate 200. Wherein, thedielectric layer 222 can be a compound layer composed of silicon oxidelayer, silicon nitride layer and silicon oxide layer in sequence fromthe bottom up. Of course, the dielectric layer 222 can also include onlysilicon oxide layer/silicon nitride layer or only a silicon oxide layer.The method of forming the dielectric layer 222 is, for example, achemical vapor deposition process.

Next, referring to FIG. 2F, a part of the tunnel oxide layer 212 and thedielectric layer 222 disposed on the bottom of the trench 210 areremoved to expose the substrate 200. Wherein, the removing method is,for example, a non-isotropic etching process. Next, a doped polysiliconlayer (not shown) is formed on the substrate 200, and a part of thedoped polysilicon layer is removed in a chemical mechanical polishingprocess to form the control gate 224. In the embodiment, note that thetunnel oxide layer 212, the floating gate 218, the dielectric layer 222,the control gate 224 and the source/drain region 220 are called a trenchdevice 225.

Next, referring to FIG. 2G, the patterned mask layer 208 is removed.Next, a dielectric layer 226 is formed on the trench device 225 and thesilicon layer 206. Wherein, the material of the dielectric layer 226 is,for example, silicon oxide. Then, a conductive layer 228 is formed onthe dielectric layer 226. Wherein, the material of the conductive layer228 is, for example, doped polysilicon. In the embodiment, theconductive layer 228 is used as word line.

Moreover, in the trench memory (as shown in FIG. 2G) provided by thepresent invention, as an isolation region is provided between thesource/drain regions in two adjacent trench devices, the abnormalelectric punch-through between two source/drain region, which affectsthe performance of the devices, can be avoided by the isolation region.

In summary, an isolation region is formed between the source/drain undertwo adjacent trench memories, therefore, with increased integration, inthe process of forming the gate with the material of doped polysilicon,the implanted dopant can be prevented from diffusing into thesource/drain region to extend the source/drain region resulting inabnormal electric punch-through between adjacent devices. Meanwhile, theproblem of short or open circuit of the devices resulting from theelectric punch-through, which may reduce the yield and reliability ofthe whole process, can also be avoided.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A manufacturing method of anti-punch-through semiconductor device,comprising: providing a substrate; forming an insulation layer on thesubstrate; patterning the insulation layer to form a plurality ofisolation regions; forming a silicon layer on the substrate to cover theisolation regions; forming a plurality of trenches between each adjacentisolation region; and forming a trench device in each trench, whereinthe trench device further comprises a source/drain region formed in thesilicon layer under the trench and disposed between two adjacentisolation regions.
 2. The method of claim 1, wherein the material of theinsulation layer comprises silicon oxide.
 3. The method of claim 1,wherein the thickness of the insulation layer is about 100 Å-1000 Å. 4.The method of claim 1, wherein the shape of the isolation regionincludes blocks or parallel stripes.
 5. The method of claim 1, whereinthe method of forming the source/drain region comprises anion-implanting method.
 6. The method of claim 1, wherein the trenchdevice includes trench memory.
 7. The method of claim 6, furthercomprising: forming a dielectric layer on the silicon layer to cover thetrench memory after the trench memory is formed; and forming aconductive layer on the dielectric layer.